Power-Oriented Test Scheduling for SOCs

The purpose of this paper is to integrate the management of power consumption to augment the parallelism of the testing activities and to reduce the testing time of SOCs. This is achieved in three parts. First, a specific scan cell is employed to reduce the switching activities during test scan stages. Secondly, a test vector reordering approach is used to reduce the test power. Finally, a test sequence expansion technique is employed to avoid the conflict of the high-power part of cores in the same session, thus as many cores can be tested concurrently. Experimental results show that the proposed approach can reduce the SOC testing time significantly.